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Description

https://www.notion.so/utat-ss/Test-Harness-Controller-Selection-aadeab4f4065491db88529fef71ed274?pvs=4

TL;DR: using the STLINK-V3MODS to meet the requirements of the FINCH-Spacecraft-TestInterface

Tasks

• [ ] Block diagram. How will you be able to fully utilize each interface, supply a robust debug interface, and ensure no damage is done to the satellite?
  • [ ] May need interfacing with @Reid Sox-Harris to clarify ICD details.
• [ ] Schematic, PCB, etc, you get the idea.

References

STLink V3 MODS Pinout

CAN Transceiver Datasheet

Notes

Block Diagram:

CAN Bus:

• Using the same CAN bus for the payelec board with the payelec layout
• I should have a footprint for termination resistors but DNP.
• Should connect the Bridge CAN to this.

GPIOs:

• There are 4 “Bridge GPIO” pins on each STLink.