Design decisions:
- decided to use only certain signals available on the chip - REG1 for power (LDO), charge and discharge protection drivers, ALERT, RESET, I2C comms, WAKE, load and pack sensing, Coulomb counting feature using a sense resistor across SRN and SRP pins, and 5 pins for the 4 cells.
- Used pins VC0,1 for the first cell, VC1,2 for the second, VC2,15 for the third and VC15,16 as per the chip datasheet specs.
- Used larger package (0402? check) resistors for current protection with maximum heat dissipation for power lines from battery cells to chip — all power from batteries to system must pass through these traces, so needed to calculate appropriate trace width based on anticipated power (3.7-4.2 per cell, maximum 4900mAh discharge rate)
- Same went for the charge and discharge protection fets - they needed a power rating high enough to withstand battery discharge and charge currents
FIRST design review happened Aug 20th, 2022.
Designer: Aurora Nowicki
Attendees: Palak Patel, Liam McGarry, Reid Sox-Harris (virtual)
Reviewer: Lorna Lan
next: incorporate design review suggestions, add test points on sch, add power LED, add wake function